uvm-testbench

There are 0 repository under uvm-testbench topic.

/ UART-Verification-using-UVM
UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.
functional-coverage uart-verification uvm-testbench wishbone-interface
Language:Verilog 7
/ BMU-Verification
UVM-based verification environment for RISC-V Bit Manipulation Unit (BMU) covering key BitManip instructions
bitmanip bitmanipulation risc-v riscv systemverilog systemverilog-hdl uvm-testbench uvm-verification
Language:SystemVerilog 1
/ Router-1x3
🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.
assertions coverage digital-design fifo fsm functional-verification hardware-designs packet-router questasim rtl-design synthesis systemverilog uvm uvm-testbench vcs verilog vlsi
Language:JavaScript
/ Router-1x3
A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
assertions coverage digital-design fifo fsm functional-verification hardware-designs questasim rtl-design synthesis systemverilog uvm uvm-testbench vcs verilog vlsi packet-router
Language:JavaScript

/ UART-Verification-using-UVM