There are 2 repositories under functional-verification topic.
A Framework for Design and Verification of Image Processing Applications using UVM
Designing means to communicate as an SPI master, being a part of AXI interface
Implements a simple UVM based testbench for a simple memory DUT.
A simple UVM testbench using UVM Connect and Octave
This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.
Apply dataclasses concept to testbench automation in Python
A simple testbench with two refmods using UVM Connect
UVM VIP for Single Port RAM Synchronous Read/Write
Verification of Advanced Encryption Standard (AES-128) Using UVM
Verification of Advanced Peripheral Bus (APB) protocol using the Universal Verification Methodology (UVM).
Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.
First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.
This article presents a technique for assembling concise, lightweight specifications and unit tests for verifying the identity of a function; the technique sacrifices completeness to enable compact and portable specifications.