mixed-signal
There are 2 repositories under mixed-signal topic.
open-neuromorphic / awesome-neuromorphic-hw
Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.
ma-laforge / InspectDR.jl
Fast, interactive Julia/GTK+ plots (+Smith charts +Gtk widget +Cairo-only images)
Language:Julia 67iic-jku / SKY130_SAR-ADC1
Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
Language:Verilog 35- Language:Python 35
manili / VSDBabySoC
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Language:Verilog 33StanfordVLSI / dragonphy2
Open Source PHY v2
Language:SystemVerilog 21NeuroFan / Algorithmic-SAR-ADC-simulation-files
HSPICE and MATLAB simulation files of a tracking SAR ADC
Language:MATLAB 19curtisseizert / Nanovoltmeter
A low noise nanovoltmeter design files and code
Language:C 18MonkHelios / RaspBerry-Pi-High-Altitude-Weather-Balloon-Hardware
Raspberry Pi powered High Altitude Weather Balloon
Language:HTML 16- Language:C++ 15
jonathanhogg / scopething
Pure Python async code for talking to the BitScope micro
Language:Python 14michaelklachko / NoisyNet
Code for "Improving Noise Tolerance of Mixed-Signal Neural Networks" https://arxiv.org/abs/1904.01705
Language:Python 12infini8-13 / riscv-ms-soc
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
Language:Verilog 10ranjith-dhananjaya / Cadence-lab-simulations
This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)
A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence
xevozen / 3bit-PWM-Generator-using-eSim
3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice
Language:Verilog 23x10e8 / cochlea_sky130
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
Language:Tcl 1- fossi_cochlea
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
Language:Verilog 1 Joschua-Conrad / Transient-Simulation-of-Dynamic-Comparator-Noise
Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.
Language:Verilog 0niliev4 / Analog-CMOS-Systems-and-circuits-for-2D-3D-Localization
This is a novel application of active analog circuits for computing the Cartesian coordinates of points ( targets ) in 2D and 3D space. Two anchors ( points ) are assumed available, with known coordinates. Optical or Infrared Angle-of-Arrival , AOA, (noisy) measurements from each anchor to the uknown target are assumed available.
Language:SourcePawn 0Pejo-306 / digital-function-generator
A digital function generator which outputs waveforms up to 10 kHz
Language:C 0Цифров генератор на сигнали с тъчскрийн
Language:C 0TheGemini135 / Lab1
Analysis and design of analog circuits, both discrete and integrated. Designs consist of amplifiers, RC circuits, bandgaps, filter circuits, circuit stability analysis, mirror circuits, and frequency compensation techniques.
0esch3r / Logisim---Proj
Some digital circuit simulations done using Logisim (which is an open source logic simulation software package)
- Language:C++
