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8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
ML-Driven Adaptive Voltage Controlled Oscillator
This project is a part of the report for my 7th semester program elective (EC-4142 Analog-VLSI).