muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard. The project consists of 4 main sections:

1. Transmitter
2. Receiver
3. PLL
4. CDR

Project Block Diagram Overview