veriloga

There are 4 repositories under veriloga topic.

muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
pll analog-design cadence-virtuoso matlab veriloga
Language:MATLAB 51
ColsonZhang / VerilogA-Wave-Generator
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
veriloga waveform-generator virtuoso simulation cadence-virtuoso
Language:Python 36
muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
adc dac cadence-virtuoso veriloga matlab
Language:MATLAB 18
muhammadaldacher / Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
adc dac cadence-virtuoso veriloga matlab
Language:MATLAB 8
akashlevy / WP-RRAM-SPICE-Model
A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
spice-model veriloga rram verilog-a compact-model well-posed
6
rpm2003rpm / vagen
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
testbench-generator verilog-a verilog-ams waveform-generator cadence cadence-virtuoso generator simulation veriloga testbench waveform
Language:Python 1
Joschua-Conrad / Transient-Simulation-of-Dynamic-Comparator-Noise
Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.
analog circuit comparator ieee mixed-signal noise simulation transient veriloga noise-estimation
Language:Verilog 0
ax0080 / Digital-Loop-Filter
Digital Loop Filter Realization
digital-signal-processing dsp verilog veriloga
Language:Verilog
nikacvet / vscode-verilogA
Language support in Visual Studio Code for VerilogA
syntax-highlighting visual-studio-code vscode-extension verilog-a veriloga
Language:TypeScript

veriloga

muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system

ColsonZhang / VerilogA-Wave-Generator

muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC

muhammadaldacher / Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC

akashlevy / WP-RRAM-SPICE-Model

rpm2003rpm / vagen

Joschua-Conrad / Transient-Simulation-of-Dynamic-Comparator-Noise

ax0080 / Digital-Loop-Filter

nikacvet / vscode-verilogA