charge-pump

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lakshmi-sathi / avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
pll clock-multiplier intellectual-property analog-circuit phase-detector charge-pump rtl2gds manufacturable ic asic
106
ranjith-dhananjaya / 20GHz-integer-N-PLL-in-65nm-CMOS-process
Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
analog capacitor charge-pump design ic-design-project inductor locking pfd pll vco frquency-divider
3
$fractional-phase-locked-loop$ adithi-su / fractional-phase-locked-loop
dsm pll fractional-pll vco charge-pump frequency-divider
Language:Verilog 1

lakshmi-sathi / avsdpll_1v8