charge-pum

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hiiask / vsd_pll
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
asic ic pll design analog-design google-skywater-pdk ngspice magic rtl2gds gds charge-pum clock-multiplier voltage-controlled-oscillator open-source open-source-hardware open-source-project
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hiiask / vsd_pll