Micro Electronics Research Laboratory

nucleusrv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

azadi-soc

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

OpenTCAM

An open-source Ternary Content Addressable Memory (TCAM) compiler.

caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

Google-Summer-of-Code

Project ideas list for Google Summer of Code.

vaquita

100DaysOfCHISEL

100 Days of CHISEL inspired by 100DaysOfRTL

magma-si

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

rv-thunder

RISC-V 32-bit CPU written in amaranth (python-lib)

Burq-Suite

An All in one RISC-V Suite.

Bitstream-Chef

cachefy

CHISEL API for plug n play connection of Caches in CHISEL designs

caravel_Ghazi_SoC_II

Lib-Analyzer

Lib Analyzer is an application which is used to analyze the cells in the liberty files.

Merl-UIT-Simulator

wenquxing22A

Clone of wangjie1450/Wenquxing22A modified for research purpose

xodus

RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL

zeusic-v

RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks

ArcheV

RISC-V RV-32i RTL Benchmark for evaluating Large Language Models.

azadi-aes

baby-kyber-accelerator

a dedicated hardware accelerator accelerating Baby Kyber Encryption operations on hardware level written in CHISEL HDL

chisel

Chisel: A Modern Hardware Design Language

magmasi_caravel

MERL-Attendance

nucleus_rv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

QSPI-Flash-Controller

riscv-oracle

rv-spidercrab

RV-SpiderCrab Dataset that is hand curated for training LLMs with everything about RISC-V ISA

tracer

CHISEL based RVFI Tracer

vulture

Vulture LLM fine-tuned with all the knowledge of RISC-V ISA.