Ethan Sifferman (sifferman)

sifferman

Geek Repo

Company:UC Santa Barbara

Location:California

Home Page:https://ethan.sifferman.dev/

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Ethan Sifferman's repositories

labs-with-cva6

Advanced Architecture Labs with CVA6

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calculator

This project serves as a recreation of the chip-on-board found in most basic 8-digit calculators.

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thesis

Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

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commercial_tools

Build Scripts for Commercial SystemVerilog Tools

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nes_controller_interface

NES Controller Interface written in Verilog-2005

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ESspice

Ethan Sifferman's Spice Simulator! Supports DC and Transient analysis of Resistors, Capacitors, Inductors, and MOSFETs.

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flip_flop_visualizer

Website to visualize the timing and schematics of flip-flops.

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basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

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CLI11

CLI11 is a command line parser for C++11 and beyond that provides a rich feature set with a simple and intuitive interface.

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common_cells

Common SystemVerilog components

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cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

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riscv-assembler

RISC-V Assembly code assembler package for Python.

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sky130_netlistsvg

This project creates transistor schematics for the sky130 PDK.

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structs

Examples of how to use structures in IEEE 1800 SystemVerilog.

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sv2v

SystemVerilog to Verilog conversion

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verilator

Verilator open-source SystemVerilog simulator and lint system

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