sifferman

labs-with-cva6

Advanced Architecture Labs with CVA6

schematics

Examples of how to Generate Schematics from SystemVerilog Synthesis Tools

calculator

This project serves as a recreation of the chip-on-board found in most basic 8-digit calculators.

thesis

Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

commercial_tools

Build Scripts for Commercial SystemVerilog Tools

nes_controller_interface

NES Controller Interface written in Verilog-2005

verilator_example

ESspice

Ethan Sifferman's Spice Simulator! Supports DC and Transient analysis of Resistors, Capacitors, Inductors, and MOSFETs.

flip_flop_visualizer

Website to visualize the timing and schematics of flip-flops.

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

CLI11

CLI11 is a command line parser for C++11 and beyond that provides a rich feature set with a simple and intuitive interface.

common_cells

Common SystemVerilog components

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

edalize

An abstraction library for interfacing EDA tools

eval-example

Using eval to test Yosys and Synlig SystemVerilog support

flip_flop_example

fpnew_sv2v

hdl-tool-installer

This script downloads all the latest releases for all the open source HDL CAD tools.

muxes

riscv-assembler

RISC-V Assembly code assembler package for Python.

rustyperalta.github.io

shadowbox

structs

Examples of how to use structures in IEEE 1800 SystemVerilog.

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

sv2v

SystemVerilog to Verilog conversion

transistor_schematics

This project creates transistor schematics for the sky130 PDK.

uvm-example

verilator

Verilator open-source SystemVerilog simulator and lint system

vivado_ddr

w21-survey