Latin American Group Integrated Circuits Development Open Source

AES128

AES128 is a IP crypto core using modes ECB/CBC/CTR using vpi to functional verification

UART

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

I2C

A i2C APB CORE MASTER AND SLAVE ASIC IP

SPACEWIRESYSTEMC

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

CRCAHB

APB

APBBRIDGE

BMAL

Basis Microletronics to Latin America

PADS

simple repo for any kind of pads used under verilog / system verilog

PWM

SPI

TIMER