The Xilinx Unisim Library Verilog available as open source under Apache 2.0.
These files coincide with the 2020.1 release of Vivado.
Apache 2.0 licensed copy of the Xilinx Unisim library.
The Xilinx Unisim Library Verilog available as open source under Apache 2.0.
These files coincide with the 2020.1 release of Vivado.
Apache 2.0 licensed copy of the Xilinx Unisim library.
Apache License 2.0