yasnakateb

PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

Chatroom

🗣 Chatroom in Rust

CGRAs

Coarse Grained Reconfigurable Arrays with Chisel3

NoCRouter

👶🏻 My first baby steps into the world of NoC

MIPSProcessor

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

WMController

✨🐾✨ A Control System for Washing Machine in Verilog HDL

AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

ChiselNotes

Chisel3 examples

Dartris

🏳️ A simple Tetris Game in Dart. Just for fun.

emacs.d

My emacs config files

MSCAllocator

A simple allocator for experimental purposes

SdramController

🛠 A SDRAM controller in Verilog HDL

UARTCommunication

☎️ UART Communication Implementation in Verilog HDL

USSalPrediction

💰 Salary prediction

aima-python

Python implementation of algorithms from Russell And Norvig's "Artificial Intelligence - A Modern Approach"

Chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Chisel7Segment

BCD to 7 Segment Decoder in Chisel3

ChiselProcessor

Multicycle processor in Chisel3

MemoryAllocators

MNISTNeuralNetwork

✍️ A simple neural network using the MNIST data set to recognize hand-written digits.

MSAllocator

OpenCVNotes

OpenCV basics in cpp

SingleProcessorSystem

💻 A Single Processor System With Gem5

Static-Timing-Analysis-Full-Course

Static Timing Analysis Full Course

TensorFlowNotes

TensorFlow for deep learning

Threshold

🖼✏️ My first baby steps into the world of image processing

yasnakateb

yasnakateb.github.io

🏠 Personal Website