umarcor

osvb

Open Source Verification Bundle for VHDL and System Verilog

hwstudio

GUI editor for hardware description designs

SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

umarcor

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

fomu-workshop

Support files for participating in a Fomu workshop

ghdl-language-server

Language server based on ghdl

cobra

A Commander for modern Go CLI interactions

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

f4pga

Documentation for F4PGA

f4pga-examples

Example designs showing different ways to use SymbiFlow toolchains.

f4pga-website

ghdl

VHDL 2008/93/87 simulator

ghdl-extended-tests

globalfoundries-pdk-libs-gf180mcu_fd_pr

Primitives for GF180MCU provided by GlobalFoundries.

godot-build-containers

Godot engine build containers

godot-docs

Godot Engine official documentation

html5liburua

HTML5-en inguruko liburuaren kode biltegia

MINGW-packages

Package scripts for MinGW-w64 targets to build under MSYS2.

neorv32

A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

neorv32-setups

:file_folder: Exemplary NEORV32 setups for various FPGA boards and toolchains.

osvvm.github.io

HTML Docs for OSVVM

OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

rticles

LaTeX Journal Article Templates for R Markdown

setup-ghdl-ci

JavaScript action for users to easily install nightly GHDL assets in GitHub Actions workflows

towncrier

Manage the release notes for your project.

Unike267-Ejercicios-Cosimulacion

Repositorio donde se mostrará los ejerciocios realizados para la asignatura "cosimulación para la verificación de sistemas sobre FPGAs".

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

yosys

Yosys Open SYnthesis Suite