microarchitecture

There are 9 repositories under microarchitecture topic.

OpenXiangShan / XiangShan
Open-source high-performance RISC-V processor
risc-v microarchitecture chisel
Language:Scala 4353
google / cpu_features
A cross platform C99 library to get cpu features at runtime.
cpu-features cpu cross-platform microarchitecture
Language:C++ 2379
Dr-Noob / cpufetch
Simple yet fancy CPU architecture fetching tool
cpus intel amd arm android linux windows microarchitecture macos
Language:C 1780
stong / how-to-exploit-a-double-free
How to exploit a double free vulnerability in 2021. Use After Free for Dummies
binary ctf double-free exploitation heap lock-free microarchitecture pwn tutorial use-after-free walkthrough
Language:Python 1297
ShaneK2 / inVtero.net
inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques
forensics hypervisor memory-dump reverse-engineering memory-hacking memory-analysis integrity-monitoring secure-hash virtual-machine attestation cloud-computing patch-management microarchitecture
Language:C# 276
microarchitecture-cheatsheet
akhin / microarchitecture-cheatsheet
X86 CPU topics overview for developers , oriented towards performance
microarchitecture x86 x86-64 cheatsheet performance low-latency amd amd64 cpu intel poster
178
CMU-SAFARI / Pythia
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
prefetcher cache-replacement branch-predictor champsim-simulator champsim-tracer reinforcement-learning machine-learning computer-architecture microarchitecture
Language:C++ 106
codexlynx / hardware-attacks-state-of-the-art
Microarchitectural exploitation and other hardware attacks.
meltdown spectre rowhammer microarchitecture infosec hardware state-of-the-art research proof-of-concept exploitation foreshadow sgx intel amd arm side-channel-attacks speculative-execution evictions cache-attack data-sampling
77
Jerc007 / Open-GPGPU-FlexGrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
gpu microarchitecture simulation-model
Language:VHDL 69
Hermes
CMU-SAFARI / Hermes
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
cache computer-architecture machine-learning perceptron perceptron-learning-algorithm prefetching microarchitecture
Language:C++ 58
libtea / frameworks
Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
aarch64 assembly c cache-attack meltdown microarchitecture ppc64 research sgx side-channel-attacks spectre x86 security
Language:C 57
Dr-Noob / peakperf
Achieve peak performance on x86 CPUs and NVIDIA GPUs
assembly avx cpu cpu-frequency cpu-microarchitecture cuda gflop gpu intrinsics microarchitecture microbenchmark nvidia performance
Language:C++ 56
HenrikBengtsson / x86-64-level
x86-64-level - Get the x86-64 Microarchitecture Level on the Current Machine
bash linux tool x86-64 cpu microarchitecture
Language:Shell 48
Dmitriy0111 / nanoFOX
A small RISC-V core (SystemVerilog)
systemverilog risc-v education programming microarchitecture cpu
Language:SystemVerilog 28
k-nuth / kth
High performance Bitcoin development platform
bitcoin btc bch ltc bitcoin-cash litecoin cpp cryptocurrency microarchitecture knuth cash high-performance cpp20
Language:Python 28
vSwarm-u
vhive-serverless / vSwarm-u
Framework that integrates the serverless benchmark suite vSwarm with gem5, the state-of-the-art research platform for system-and microarchitecture.
gem5 microarchitecture research serverless simulation vswarm
Language:Python 23
b-shi / PMC-PMI
Performance Counter Measurements at the cycle granularity
microarchitecture linux-kernel-module performance-counters cpu-profiling
Language:C 16
kuby1412 / RISC-V-MYTH-Workshop
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
riscv tl-verilog microarchitecture cpu rv32i verilog pipelines microprocessors rtl
Language:C 16
FISC-Project / FISC-VHDL
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
cpu armv8 microarchitecture fisc computer-architecture vhdl c cpp intel arm
Language:VHDL 14
jiegec / cpu-micro-benchmarks
CPU micro benchmarks
benchmark microarchitecture
Language:C++ 14
yonseicasl / Kite
Kite: Architecture Simulator for RISC-V Instruction Set
risc-v simulator architecture five-stage pipeline model education assembly computer-architecture microarchitecture pipelining branch-prediction cache instruction-set instruction-set-architecture memory instruction-dependency
Language:C++ 14
AliLRS / RISC-V_Microprogrammed
computer-architecture microarchitecture microprogrammed microprogrammed-control-unit risc-v riscv
Language:SystemVerilog 13
dominiksalvet / risc63
Custom 64-bit pipelined RISC processor
64-bit custom processor isa architecture pipeline microarchitecture rtl vhdl ghdl makefile risc cpu open-source hardware alu interrupts testbench thesis bachelor-thesis
Language:VHDL 13
toor1245 / cpu_features.NET
.NET version of google/cpu_features to get cpu info at runtime.
dotnet cpuid cpu x86-64 microarchitecture arm xamarin net-standard aarch64 cross-platform arm64 arm32v7 android ios macos linux windows freebsd
Language:C# 12
mamadaliev / sequent
Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog
fpga microarchitecture system-verilog
Language:Verilog 10
dhschall / gem5-fdp
Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
microarchitecture prefetching simulator
Language:C++ 9
evanlissoos / OISC
One Instruction Set Computer
microarchitecture cpu-emulator cpu-model simulation killmeplz
Language:Python 9
saintube / gem5-dscp
DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.
gem5 microarchitecture cache
Language:C++ 9
dominiksalvet / limen-alpha
Dual-core 16-bit RISC processor
dual-core 16-bit processor isa architecture microarchitecture custom risc cpu vhdl rtl fpga hardware alu circuit interrupts synchronization multicore basys2 simulation
Language:VHDL 8
leepoly / chisel-pobu-cache
microarchitecture chisel3 computer-architecture cpu-model
Language:Verilog 7
Sacusa / LC-3
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".
lc3b microarchitecture computer-architecture vlsi vhdl educational processor microprocessor
Language:VHDL 7
aecsocket / cpu-features-java
Java bindings for Google cpu_features
cpu cpu-features cross-platform java jni microarchitecture
Language:Java 5
Dmitriy0111 / nanoFOX_VHDL
A small RISC-V core (VHDL)
vhdl risc-v education programming microarchitecture cpu
Language:VHDL 5
hushon / Tiny-RISCV-CPU
Mini RISC-V CPU
risc-v microarchitecture cpu
Language:Verilog 5
lywangj / Modelling_Apple_M1_CPU_Architecture
2021-22 Summer Project in Computer Science
apple m1 microarchitecture processor-simulator
Language:Assembly 5
hoseinyavarzadeh / archsec-deadlines
:alarm_clock: Computer Architecture and Security Conference Deadline Countdowns (Based on AI Deadlines)
computer-architecture computer-security conference-deadlines microarchitecture
Language:JavaScript 3

microarchitecture

OpenXiangShan / XiangShan

google / cpu_features

Dr-Noob / cpufetch

stong / how-to-exploit-a-double-free

ShaneK2 / inVtero.net

akhin / microarchitecture-cheatsheet

CMU-SAFARI / Pythia

codexlynx / hardware-attacks-state-of-the-art

Jerc007 / Open-GPGPU-FlexGrip-

CMU-SAFARI / Hermes

libtea / frameworks

Dr-Noob / peakperf

HenrikBengtsson / x86-64-level

Dmitriy0111 / nanoFOX

k-nuth / kth

vhive-serverless / vSwarm-u

b-shi / PMC-PMI

kuby1412 / RISC-V-MYTH-Workshop

FISC-Project / FISC-VHDL

jiegec / cpu-micro-benchmarks

yonseicasl / Kite

AliLRS / RISC-V_Microprogrammed

dominiksalvet / risc63

toor1245 / cpu_features.NET

mamadaliev / sequent

dhschall / gem5-fdp

evanlissoos / OISC

saintube / gem5-dscp

dominiksalvet / limen-alpha

leepoly / chisel-pobu-cache

Sacusa / LC-3

aecsocket / cpu-features-java

Dmitriy0111 / nanoFOX_VHDL

hushon / Tiny-RISCV-CPU

lywangj / Modelling_Apple_M1_CPU_Architecture

hoseinyavarzadeh / archsec-deadlines