A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Repository from Github https://github.comaryan-programmer/axi_gen_and_sum_primes_fpgaRepository from Github https://github.comaryan-programmer/axi_gen_and_sum_primes_fpga
