raleighlittles / Basys3CountdownClock

Extremely basic countdown clock project for the Basys 3 FPGA development board.

verilog hdl xilinx vivado xdc seven-segment-display fpga basys-3 basys3

About

Very basic implementation of a countdown clock, written for the Basys 3 FPGA trainer board.

Uses the 4 7-segment displays available to start counting down from 9999 to 0 and then back to 9999 again.

Setup

Pre-requisites

Vivado Design Suite

Instructions

Import source and constraints file
Run Synthesis
Run Implementation
Generate bitstream

About

Extremely basic countdown clock project for the Basys 3 FPGA development board.

verilog hdl xilinx vivado xdc seven-segment-display fpga basys-3 basys3

Languages

Language:Verilog 100.0%