Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
Repository from Github https://github.comPrajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7segRepository from Github https://github.comPrajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg
