There are 3 repositories under cache-simulator topic.
a high performance library for building cache simulators
SST Architectural Simulation Components and Libraries
A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.
A C++11 simulator for a variety of CDN caching policies.
cache analysis platform developed at Emory University and CMU
Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
This cache simulator is used in order to simulate substitutions in cache using replacement policies (FIFO and LRU) and write back into the cache (using the write-allocate policy).
A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.
Computer architecture project : Cache simulator with LRU replacement policy
Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.
OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP. Integrated with Sniper simulator.
Contains implementations of cache-optimized and external memory algorithms.
Simulator of experiments presented in "Enabling Long-term Fairness in Dynamic Resource Allocation", ACM SIGMETRICS 2023.
Computer architecture related projects
WPI CS2011 Assembly Assignments for B-term 2017
Set of MIPS assembly programs to help us find a secret cache configuration (cache size, block size and associativity).
Direct Mapped and N-Way set associative cache Simulator in C/C++ for L1 cache in Processors
A modular implementation of three level Cache Hierarchy
A 3-level cache simulator for SPEC traces with various inclusion and block replacement policies
PKU computer organization and architecture memory hierarchy simulator LAB
AUT Computer Architecture Cache Simulator project