mortbopet

Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

VSRTL

Visual Simulation of Register Transfer Logic

NetCracker

NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between switchboxes

mlir-interactive

Qt based UI for visual and interactive composition and execution of MLIR compilation flows.

VelonaCore

A VHDL implementation of a single-cycle Leros core

riscv-asm-manual

RISC-V Assembly Programmer's Manual

circt

Circuit IR Compilers and Tools

QtWasmThreaded

Prebuilt version of the latest Qt for WebAssembly, with thread support enabled

libelfin

C++11 ELF/DWARF parser

nodeeditor

Qt Node Editor. Dataflow programming framework

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Troeffelheltene

Trøffelheltenes opskriftseventyr

VelonaMP

verilator

Verilator open-source SystemVerilog simulator and lint system

better-enums

C++ compile-time enum to string, iteration, in a single header file

calyx

Intermediate Language (IL) for Hardware Accelerator Generators

Catch2

A modern, C++-native, header-only, test framework for unit-tests, TDD and BDD - using C++11, C++14, C++17 and later (or C++03 on the Catch1.x branch)

circt-www

CIRCT website

clang-tools-extra

Mirror of official clang-tools-extra git repository located at http://llvm.org/git/clang-tools-extra. Updated every five minutes.

copilot-docs

Documentation for GitHub Copilot

images

Docker images for the CIRCT project

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

mortbopet.github.io

Ripes WASM host site

Polygeist

protobuf-matchers

Protocol buffer matchers for gMock/gTest

SparseAddressSpace

A datastructure for efficiently simulating a (potentially unlimited) address space.

substrait-cpp

substrait-mlir-contrib

subsurface

This is the official upstream of the Subsurface divelog program

treadle

Chisel/Firrtl execution engine