pulpino

There are 0 repository under pulpino topic.

klessydra / T13x
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
klessydra t13x t03x t02x riscv pulpino superscalar vector-processor accelerator simd mimd
Language:VHDL 43
klessydra / T02x
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
klessydra t02x t03x t13x riscv pulpino
Language:VHDL 20
klessydra / T03x
A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
klessydra t03x t02x t13x riscv pulpino
Language:VHDL 12
kactus2 / pulpinoexperiment
IP-XACT packaging of Pulpino by pulp-platform.org: https://github.com/pulp-platform/pulpino
pulpino risc-v ip-xact example-project
Language:Verilog 10
rafafigueredoviana / RISCV_MCU_CYCLONEV
A basic implementation of the RISCV core into a DE10nano FPGA board.
riscv fpga altera-fpga pulpino de10nano de10-nano
Language:SystemVerilog 7
coastalwhite / pulpino-top-level-cw305
The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core
chipwhisperer pulpino riscv
Language:Verilog 4
cad-polito-it / pulpino_ri5cy_stls
Stuck-At Software Test Libraries for the pulpino-ri5cy SoC
pulpino ri5cy risc-v-assembly sbst stl
Language:Assembly 3
neumann_fpga
SubhamRath / neumann_fpga
FPGA emulation for project neumann.
risc-v pulpino silicon controller fpga

pulpino

klessydra / T13x

klessydra / T02x

klessydra / T03x

kactus2 / pulpinoexperiment

rafafigueredoviana / RISCV_MCU_CYCLONEV

coastalwhite / pulpino-top-level-cw305

cad-polito-it / pulpino_ri5cy_stls

SubhamRath / neumann_fpga