whutddk

RiftCore

RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

Rift2Core

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

whutddk.github.io

BitcoinWhitePaper

Blockchain-dark-forest-selfguard-handbook

Blockchain dark forest selfguard handbook. Master these, master the security of your cryptocurrency.

caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.

caravel_user_project

https://caravel-user-project.readthedocs.io

CnC_Red_Alert

Command and Conquer: Red Alert

constellation

A Chisel RTL generator for network-on-chip interconnects

DARC

Decentralized Autonomous Regulated Company (DARC), a company virtual machine that runs on any EVM-compatible blockchain, with on-chain law system, multi-level tokens and dividends mechanism.

evil.js

Use with caution

jtdx

JTDX

Knowledge-Base

Knowledge Base 慢雾安全团队知识库

mac

mpwData

This is a repo storing the files in each MPW

OSSRH-81803

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Rift2Fake_gf180_mpw0

Rift2Fake_sky130_resubmission

Rift2Go_2300_GF180_MPW0

Rift2Go_2300_GF180_MPW1

Rift2Go_2300_Sky130_MPW8

Rift2Go_2310_Sky130_MPW7

Rift2Go_2320_Sky130_MPW8

Rift2Go_2330_Sky130_MPW8

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-test-env

riscv-torture

RISC-V Torture Test

Rocketchip-sub4mac

ysyx-workbench