whutddk

RiftCore

RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

Rift2Core

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

whutddk.github.io

BitcoinWhitePaper

caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.

caravel_user_project

https://caravel-user-project.readthedocs.io

chisel3

Chisel 3: A Modern Hardware Design Language

constellation

A Chisel RTL generator for network-on-chip interconnects

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

DARC

Decentralized Autonomous Regulated Company (DARC), a company virtual machine that runs on any EVM-compatible blockchain, with on-chain law system, multi-level tokens and dividends mechanism.

evil.js

Use with caution

jtdx

JTDX

mpwData

This is a repo storing the files in each MPW

OSSRH-81803

Rift2Fake_gf180_mpw0

Rift2Fake_sky130_resubmission

Rift2Go_2300_GF180_MPW0

Rift2Go_2300_GF180_MPW1

Rift2Go_2300_Sky130_MPW8

Rift2Go_2310_Sky130_MPW7

Rift2Go_2320_Sky130_MPW8

Rift2Go_2330_Sky130_MPW8

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-online-asm

RISC-V Online Assembler using Emscripten, Gnu Binutils

riscv-p-spec

RISC-V Packed SIMD Extension

riscv-test-env

riscv-torture

RISC-V Torture Test

sifive-blocks

Common RTL blocks used in SiFive's projects

ysyx-workbench