Beast code in Giters

k-sva's repositories

The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )

Language:VerilogMIT12 20

GUI based UVM Test Environment generation tool

Language:PythonMIT7 20

RTL design for the AMBA AHB protocol.

Language:SystemVerilogMIT6 20

Verilog parallel CRC generation module with custom polynomial and variable width

Language:PerlMIT3 10

All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

Language:VerilogMIT3 10

Automated script to generate a generic UVM testbench with compatible makefile and internal scripts.

MIT2 10

VGA controller RTL ( soft ip ) in Verilog

Language:VerilogMIT2 10

It's a simple verilog based MIPS microarchitecture hardware design.

Language:SystemVerilogMIT2 20

Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )

Language:Shell2 10

RISC-V ( 32b / Single Cycle ) - "RV32I"

Language:ShellMIT2 10

Custom polynomial ( variable width ) LFSR ( Galios/Fib ) generator

Language:ShellMIT1 10

Verilog serial CRC generation module with custom polynomial and variable width

Language:ShellMIT1 10

Linux Scripts & Settings ( tcshrc and vim )

Language:Vim Script010

Dummy repo to practice git commands

010