Julio (JN513)

JN513

Geek Repo

Company:Embarcações Unicamp @LSC-Unicamp

Location:Campinas, São Paulo, Brasil

Home Page:https://bzoide.dev

Twitter:@JulioNunesAvel4

Github PK Tool:Github PK Tool


Organizations
LSC-Unicamp
Scarlateoficial

Julio's repositories

Risco-5

Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.

Language:VerilogLicense:CERN-OHL-P-2.0Stargazers:6Issues:0Issues:0

Google_search_API

API desenvolvida em Flask com o Intuito de realizar buscas no google e retornar em formato Json.

Language:PythonLicense:MITStargazers:4Issues:1Issues:0

riscv-isa-ci

CI/CD for RISC-V Cores

Language:VerilogLicense:GPL-3.0Stargazers:4Issues:1Issues:0
Language:QMLLicense:MITStargazers:3Issues:0Issues:0

Pequeno-Risco-5

Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.

Language:VerilogLicense:MITStargazers:3Issues:1Issues:0

esp32_uart_sx1276

Biblioteca escrita para utilização de modulo LoRa com comunicação via UART no ESPIDF

Language:CLicense:GPL-3.0Stargazers:2Issues:1Issues:5

biriscv

32-bit Superscalar RISC-V CPU

Language:VerilogLicense:Apache-2.0Stargazers:1Issues:0Issues:0

caninos-sdk

Facilitando o uso da placa Labrador. 🐶💻

Language:PythonLicense:MITStargazers:1Issues:0Issues:0

color_image_cli

Cliente de linha de comando para transformar imagens coloridas em preto e branco e escala de cinza

Language:PythonStargazers:1Issues:1Issues:0

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Language:VerilogLicense:BSD-3-ClauseStargazers:1Issues:0Issues:0

estudos_verilog

Exemplos feito em verilog para estudos

Language:VerilogLicense:MITStargazers:1Issues:1Issues:0

Grande-Risco-5

Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.

Language:VerilogLicense:CERN-OHL-P-2.0Stargazers:1Issues:1Issues:0

lmic-esp-idf

A good port of the LMIC LoRaWAN library to esp-idf

Language:CStargazers:1Issues:0Issues:0
Language:PythonLicense:NOASSERTIONStargazers:1Issues:0Issues:0

meson

The Meson Build System

Language:PythonLicense:Apache-2.0Stargazers:1Issues:0Issues:0

minerva

A 32-bit RISC-V soft processor

Language:PythonLicense:NOASSERTIONStargazers:1Issues:0Issues:0

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogLicense:ISCStargazers:1Issues:0Issues:0
Language:PythonStargazers:1Issues:0Issues:0

RISC-V-Implementation-Verilog

Repositório do grupo 3 (Grupo Cessar) de PCS3115

Language:VerilogStargazers:1Issues:0Issues:0

riscv-steel

Free collection of RISC-V IP cores.

Language:VerilogLicense:MITStargazers:1Issues:0Issues:0

serv

SERV - The SErial RISC-V CPU

Language:VerilogLicense:ISCStargazers:1Issues:0Issues:0
Language:PythonLicense:GPL-3.0Stargazers:1Issues:1Issues:0

tinyriscv

A very simple and easy to understand RISC-V core.

License:Apache-2.0Stargazers:1Issues:0Issues:0

dv-cpu-rv

A harvard architecture CPU based on RISC-V.

License:GPL-3.0Stargazers:0Issues:0Issues:0

explore

Community-curated topic and collection pages on GitHub

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

nerv

Naive Educational RISC V processor

License:NOASSERTIONStargazers:0Issues:0Issues:0

nes_colorlight

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

License:GPL-3.0Stargazers:0Issues:0Issues:0

Risco_5-tiny_tapeout

Risco 5 Tiny tapeout

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0