sequence-detector

There are 1 repository under sequence-detector topic.

sumukhathrey / Verilog_ASIC_Design
Verilog for ASIC Design
hardware hardware-modelling verilog sequence-detector testbench rtl counter adder gates
Language:Verilog 22
Shahriar-0 / Digital-Logic-Design-Lab-Experiments-S2023
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
accelerator function-generator sequence-detector verilog
Language:Verilog 10
carminecolucci / Sequence-Detector-FSM
Generates a Finite State Machine to detect a binary sequence
finite-state-machine fsm sequence-detector state-machine
Language:C 2
hansinahuja / Hardware-Based-Teaching-Aid
A hardware-based teaching aid for students to get familiarized with sequential logic using Basys FPGA boards.
verilog verilog-project sequential-logic quine-mccluskey bcd sequence-detector teaching-tool
Language:HTML 2
minecraftdixit / Digital-ASIC-LAB
Verilog Codes for various Design
adder fifo max-pooling multiplication one-detector pipeline reconfigurable-matrix-adder sequence-detector system-verilog uvm verilog verilog-hdl
Language:SystemVerilog 2
ramprasadkillari / CS254-Digital-Logic-Design-Lab
All my submissions to assignments in CS254 - Digital Logic Design Lab ( Spring Course 2019 IIT BOMBAY)
elevator-simulation sdn-controller sequence-detector stopwatch traffic-signal-simulation vendingmachine vhdl
Language:Rich Text Format 2
HsuChiChen / ncku-logic-design
sequence detector with overlapped 2 patterns 010111 or 1101
sequence-detector hardware-acceleration digital-logic-design
Language:Verilog 1
ShashankVM / overlapping-sequence-detector-1011-mealy-sv
Mealy Finite State Machine type overlapping sequence detector of "1011" in SystemVerilog.
finite-state-machine sequence-detector systemverilog
Language:SystemVerilog 1
ferrispnugraha / 0010-and-100-Sequence-Detector
Mealy Machine with VHDL
vhdl vivado sequence-detector mealy-machine
Language:VHDL 0
levyashvin / verilog_codes
basic implementation of logic structures using verilog (revising github)
verilog-testbenches d-flipflop full-adder full-subtractor half-subtractor jk-flipflop pipo piso priority-encoder registers sequence-detector sipo siso sr-flip-flop synchronous-counter t-flipflop
Language:Verilog 0
utkarshad21 / FSM-Sequence-Detector-using-Verilog
FSM: Sequence Detector using Verilog HDL
fsm hdl mealy-fsm mealy-machine sequence-detection sequence-detector verilog verilog-code verilog-hdl verilog-project sequence-detector-11010
Language:Verilog 0
sushi0706 / verilog-mini-projects
Verilog Mini Projects
verilog verilog-project alarm-clock barrel-shifter booth-multiplication carry-look-ahead-adder fifo lfsr sequence-detector traffic-light-controller vending-machine voting-machine
Language:Verilog