TimRudy

ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

yosys

Yosys Open SYnthesis Suite

electric-cpu

Home-designed CPU, and a documented process to build it

icestudio

:snowflake: Visual editor for open FPGA boards

open-fpga-verilog-tutorial

Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

angular-tuenkd-custom-input

Created with StackBlitz ⚡️

events-app-external

events-app-internal

saturn-datepicker

Angular Material Datepicker with range selection

TimRudy.github.io

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