Sidhant priyadarshi (sidhantp1906)

sidhantp1906

Geek Repo

Company:KLE Technological University

Location:bihar

Home Page:linkedin.com/in/sidhant-priyadarshi-028612185/

Github PK Tool:Github PK Tool

Sidhant priyadarshi's repositories

4-Request-First-Come-First-Serve-Arbiter

4 request first come first serve arbiter design using verilog HDL

Language:VerilogLicense:Apache-2.0Stargazers:3Issues:1Issues:0

Adcanced_Digital_Logic_Design-01fe19bec187

Lab projects using Verilog HDL

Language:VerilogLicense:Apache-2.0Stargazers:2Issues:1Issues:0

binary-to-csd

verilog code to covert binary number into canonical signed digit(csd)

Language:VerilogLicense:Apache-2.0Stargazers:2Issues:1Issues:0

RTC-Real-Time-Clock-

Design of real time clock(RTC) using Verilog HDL

Language:VerilogLicense:Apache-2.0Stargazers:2Issues:1Issues:0

TicTacToe

TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board

Language:VerilogLicense:MITStargazers:2Issues:1Issues:0

AMBA4-APB

Advanced Pheripheral Bus design using verilog HDL

Language:VerilogLicense:Apache-2.0Stargazers:1Issues:1Issues:0

csd-multiplier-using-booth-technique

csd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.

Language:VerilogLicense:MITStargazers:1Issues:1Issues:0

IEEE-latex-report

IEEE-latex-report for 32-bit CSD multiplier

License:Apache-2.0Stargazers:1Issues:1Issues:0

Resume

Contains my resume

Vending-machine

Soda & Water Vending Machine with Return & Refund functionality designed using Verilog HDL

License:Apache-2.0Stargazers:1Issues:1Issues:0

4-bit-first-divider

4 bit divider design using first divider algorithm

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0

8-bit-first_multiplier

verilog design of first multiplier design and architecture

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0

Analog-Hackathon-Data-Encryption-

2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology

License:Apache-2.0Stargazers:0Issues:1Issues:0

analog-to-digital-clock-generator

Here i designed a converter circuit which converts analog sine signal to digital clock signal.This is my personal work which suddenly came into my mind so i designed.I used half wave rectifier circuit with filter to get +ve half of sine wave and then used comparator to convert that into square wave which is digital clock output.

License:Apache-2.0Stargazers:0Issues:1Issues:0

Automation-with-python

basic projects using python

Language:PythonLicense:MITStargazers:0Issues:1Issues:0
Language:Jupyter NotebookLicense:Apache-2.0Stargazers:0Issues:1Issues:0

eSIM-Marathon

designed a simple D-flipflop from JK-flipflop using eSIM and SKY130nm pdk

License:MITStargazers:0Issues:1Issues:0

FCFS_Arbiter_Design_And_Verification

Design and verification of first come first serve arbiter

Language:SystemVerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0

googlecolab_python

learning python

Language:Jupyter NotebookLicense:Apache-2.0Stargazers:0Issues:1Issues:0

googlekickstart2020

practicing 2020 google kickstart questions using python

Language:PythonLicense:Apache-2.0Stargazers:0Issues:1Issues:1

guess-game-using-python

i have designed a beautiful guess game using python. Lerning python part3

Language:Jupyter NotebookLicense:Apache-2.0Stargazers:0Issues:1Issues:0

lottery-game

lottery game using python

Language:Jupyter NotebookLicense:MITStargazers:0Issues:0Issues:0

OpenCV

learning opencv basics

Language:PythonLicense:Apache-2.0Stargazers:0Issues:1Issues:0

PulseWidthModulation

PWM module using verilig HDL in XILINX ISE

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0
Language:VerilogLicense:MITStargazers:0Issues:1Issues:0

RV32I

I worked personally on designing rv32i processor for some of the instructions like add,addi,sub,etc..

Language:VerilogLicense:MITStargazers:0Issues:1Issues:0

sidhantp1906

Config files for my GitHub profile.

Language:Jupyter NotebookStargazers:0Issues:1Issues:0

social-distance-maintainer

social distance maintainer using arduino uno R3

License:MITStargazers:0Issues:1Issues:0

Starting-with-ML-

basic problem statements and solution of machine learning

Language:PythonLicense:Apache-2.0Stargazers:0Issues:1Issues:0

UART

UART implementation using Verilog HDL

Language:VerilogLicense:MITStargazers:0Issues:1Issues:0