hl271 / uart_with_fifo

Verilog implementation of UART protocol with integrated FIFO buffer

uart_with_fifo

This project is tested and implemented in FPGA Altera DE2-115

Verilog implementation of UART protocol with integrated FIFO buffer

Language:Verilog 84.9%Language:Python 8.0%Language:SystemVerilog 5.0%Language:Stata 2.1%