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liuqdev / 8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

Repository from Github https://github.comliuqdev/8-bits-RISC-CPU-VerilogRepository from Github https://github.comliuqdev/8-bits-RISC-CPU-Verilog

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