Luke Wren's repositories
ChristmasSoC
Dual-core RISC-V SoC with JTAG, atomics, SDRAM
TwoWireDebug
Yet Another Debug Transport
tt02-whisk-serial-processor
Whisk: 16-bit serial processor for TT02
fpgascripts
Loose collection of scripts for FPGA work
riscv-formal
RISC-V Formal Verification Framework
gambatte-core
Fork of https://github.com/sinamas/gambatte with Pokemon speedrunning-related changes.
Hazard3-SWD-SoC
Example Hazard3 + OpenDAP RISC-V SWD SoC integration
riscv-isa-manual
RISC-V Instruction Set Manual
CQ-editor
CadQuery GUI editor based on PyQT
Language:PythonApache-2.0000
embench-iot
The main Embench repository