Wren6991

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Cambridge, UK

Luke Wren's repositories

PicoDVI

Bitbanged DVI on the RP2040 Microcontroller

Language:CBSD-3-Clause1048 47 45

RISCBoy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Language:C224 18 3

asciiwave

Turn WaveDrom timing diagrams into ASCII art

Language:PythonBSD-3-Clause128 9 1

Hazard3

3-stage RV32IMACZb* processor with debug

Language:VerilogApache-2.070 8 5

libfpga

Reusable Verilog 2005 components for FPGA designs

Language:VerilogNOASSERTION25 50

SmolDVI

Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs

Language:VerilogCC0-1.022 40

Hazard2

Smol 2-stage RISC-V processor in nMigen

Language:PythonBSD-3-Clause21 60

ChristmasSoC

Dual-core RISC-V SoC with JTAG, atomics, SDRAM

Language:VerilogApache-2.019 40

OpenDAP

Language:C++CC0-1.018 40

TwoWireDebug

Yet Another Debug Transport

Language:VerilogCC0-1.018 50

Hazard5

5-stage RISC-V CPU, originally developed for RISCBoy

Language:VerilogNOASSERTION11 50

tt02-whisk-serial-processor

Whisk: 16-bit serial processor for TT02

Language:VerilogApache-2.011 10

Bico

Dual-RP2040 development board with built-in debug

CC0-1.06 10

fpgascripts

Loose collection of scripts for FPGA work

Language:Python5 30

picosystem-experiments

Language:CBSD-3-Clause3 30

riscv-formal

RISC-V Formal Verification Framework

Language:VerilogISC3 20

rvcpp

Language:C++BSD-3-Clause3 20

virtual-jtag-dtm

Language:C3 20

49er

Minimal Python text editor using curses

Language:Python1 20

ecp5_jtag

Use ECP5 JTAG port to interact with user design

Language:Verilog1 20

gambatte-core

Fork of https://github.com/sinamas/gambatte with Pokemon speedrunning-related changes.

Language:AssemblyGPL-2.01 20

Hazard3-SWD-SoC

Example Hazard3 + OpenDAP RISC-V SWD SoC integration

Language:VerilogApache-2.01 20

riscv-isa-manual

RISC-V Instruction Set Manual

Language:TeXCC-BY-4.01 20

riscv-tests

Language:CNOASSERTION1 20

buildroot

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.

Language:MakefileNOASSERTION010

embench-iot

The main Embench repository

Language:CGPL-3.0020

Hazard1

Minimal RV32I processor with register file in RAM

Language:Verilog010

opensbi

RISC-V Open Source Supervisor Binary Interface

Language:CNOASSERTION000

riscv-arch-test

Language:AssemblyApache-2.0010

riscv-test-env

Language:CNOASSERTION000