shahed22 / Dadda-8-bit

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Repository from Github https://github.comshahed22/Dadda-8-bit

algorithms algorithms-implemented asic-design fpga fpga-programming fulladder halfadder multiplier multipliers rtl rtl-design verilog

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The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

algorithms algorithms-implemented asic-design fpga fpga-programming fulladder halfadder multiplier multipliers rtl rtl-design verilog

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