This repository builds upon the work of RV32I_Single_Cycle_CPU by extending the RISC-V Data Path to support a 5-Stage Pipelined CPU architecture. It simplifies the RV32I Single Cycle CPU and enhances it into a more efficient pipelined design.
Processor Design of RV32I 5-Stage Pipelined CPU
This repository builds upon the work of RV32I_Single_Cycle_CPU by extending the RISC-V Data Path to support a 5-Stage Pipelined CPU architecture. It simplifies the RV32I Single Cycle CPU and enhances it into a more efficient pipelined design.
Processor Design of RV32I 5-Stage Pipelined CPU