processordesign

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jracevedob / Processor-Design
In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.
verilog processordesign wishbone zmc highperformance
Language:Verilog 4

jracevedob / Processor-Design