Chair for Embedded Security (emsec)

Chair for Embedded Security

emsec

Organization data from Github https://github.com/emsec

Location:Germany

Home Page:http://emsec.rub.de

GitHub:@emsec

Chair for Embedded Security's repositories

ChameleonMini

The ChameleonMini is a versatile contactless smartcard emulator compliant to NFC. The ChameleonMini was developed by https://kasper-oswald.de. The device is available at https://shop.kasper.it. For further information see the Getting Started Page https://rawgit.com/emsec/ChameleonMini/master/Doc/Doxygen/html/_page__getting_started.html or the Wiki tab above.

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hal

HAL – The Hardware Analyzer

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SCATools

Open tools for side-channel analysis and related techniques. Currently, this repository contains: 1) A near-field EM probe amplifier circuit

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ImpeccableCircuits

Hardware designs for fault detection

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ConFuzz

ConFuzz is an advanced FPGA configuration engine fuzzing and rapid prototyping framework based on boofuzz and OpenOCD.

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VerFI

Beta Version of Cryptographic Fault Diagnosis Tool (VerFI)

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hal-benchmarks

Benchmark suite for HAL

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unsupervised-ic-sem-segmentation

Implementation of our paper 'Towards Unsupervised SEM Image Segmentation for IC Layout Extraction'

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QESA_ZK

Code for our CCS paper "Efficient zero-knowledge arguments in the discrete log setting, revisited"

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ReverSim

An open-source browser environment to empirically study human aspects in hardware reverse engineering.

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TI-PUF

Hardware designs for TI-PUF

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riscv-ucode

Microcoded RISC-V implementation

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ImpeccableCircuitsII

Hardware designs for fault correction

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boofuzz

A fork and successor of the Sulley Fuzzing Framework

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reversim-circuits

Library of circuits for use with ReverSim, our open-source netlist reverse engineering simulation

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EK_feistel

Qt GUI application which illustrates a round of Feistel encoding in DES algorithm

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homebrew-hal

Homebrew hal tap

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unsupervised-ic-sem-segmentation-extended

Implementation of our extended paper 'Advancing Training Stability in Unsupervised SEM Image Segmentation for IC Layout Extraction'

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