verilog-a

There are 1 repository under verilog-a topic.

pascalkuthe / OpenVAF
An innovative Verilog-A compiler
compiler eda rust verilog-a
Language:Rust 100
ACMmodel / MOSFET_model
A simple MOSFET model with only 5-DC-parameters for circuit simulation
circuitsimulation icdesign mosfet verilog-a gf180mcu ihp open-source sky130 transistor-modeling
30
akashlevy / pyxbar
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
python spice hspice netlist waveform generator simulation circuit memory-design rram nvm verilog-a testbench
Language:SourcePawn 11
akashlevy / WP-RRAM-SPICE-Model
A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
spice-model veriloga rram verilog-a compact-model well-posed
6
gnucap / gnucap-adms
defunct. use repo on savannah
adms verilog-a gnucap
5
pouryahoseini / Genetic-Algorithm-Processor
A digital genetic algorithm processor
circuit cmos customsim digital evolutionary-computation genetic-algorithm hsim optimization processor spice verilog-a
Language:Verilog 3
NVerilog / NVerilogParser
A Verilog-AMS parser for .NET
verilog-ams verilog verilog-a parser dotnet csharp
Language:C# 2
thennen / Synaptogen
A fast generative model for stochastic memory cells
circuit-simulation emerging-technology gpu julia machine-learning modeling neuromorphic-hardware reram simulation verilog-a
Language:Julia 2
pyadms / pyadms
Python Automatic Device Model Synthesizer
python verilog-a verilog-ams
Language:C++ 1
rpm2003rpm / vagen
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
testbench-generator verilog-a verilog-ams waveform-generator cadence cadence-virtuoso generator simulation veriloga testbench waveform
Language:Python 1
posvirus / RTE-Sim
Compact model for light propagation simulation in fNIRS systems
compactmodelling fnirs simulink verilog-a
0
nikacvet / vscode-verilogA
Language support in Visual Studio Code for VerilogA
syntax-highlighting visual-studio-code vscode-extension verilog-a veriloga
Language:TypeScript
rpm2003rpm / stg2veriloga
converts a stg (.g file generated by workcraft) to a verilogA model
asynchronous digital-logic-design generator stg verilog-a simulation
Language:Python