This is a demo for still image compression application. Based on the paper “An efficient adaptive binary range coder and its VLSI architecture” published on IEEE Transactions on circuit and system for video technology, vol. 25, no.8, pp.1435-1446, 2015, we merged our arithmetic coder (AC) in the JPEG2000 framework to replace MQ. We implemented software and hardware on FPGA. Then we decided to publish it for research and evaluation. For detailed description, see specification.pdf file.