Akash Levy (akashlevy)

akashlevy

Geek Repo

Company:Silimate, Inc.

Location:San Francisco, CA

Home Page:akashlevy.com

Twitter:@akashlevy

Github PK Tool:Github PK Tool

Akash Levy's repositories

Deep-Learn-Oil

Deep learning tools for predicting oil well data

Language:PythonStargazers:87Issues:19Issues:0

NEM-Relay-CAD

Parametric NEM relay design with layout generation (KLayout: GDSII, DXF), FEM (Ansys/COMSOL), SPICE models, Liberty models, and more

Language:HTMLLicense:MITStargazers:17Issues:8Issues:0

NEM-Relay-CGRA

Jade CGRA using NEM relay interconnect fabric. Related repositories: NEM-Relay-CGRA-Flow, NEM-Relay-CAD

Language:VerilogLicense:BSD-3-ClauseStargazers:8Issues:3Issues:0

RRAM-Relaxation-Master-Model

Repository containing the data and the code for the RRAM relaxation master model

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RRAM-DNN-Quantized

Evaluating accuracy on quantized DNNs using RRAM as weight storage

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RRAM-RADAR-Tuning

Code and repository for RRAM RADAR programming method: https://doi.org/10.1109/TED.2021.3097975

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ember-python

EMBER Python scripts for post-silicon validation and testing via SPI

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Safeway-Vax-Checker

A script to check for vaccine availability at a Safeway near you

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gem5-nvm-study

Using Gem5 to study non-volatile memories in a CPU memory hierarchy

Language:Jupyter NotebookLicense:MITStargazers:1Issues:2Issues:0

NEM-Relay-CGRA-Flow

Mflowgen flow for physical design and signoff evaluations of the NEM Relay CGRA. Related repositories: NEM-Relay-CAD, NEM-Relay-CGRA

License:MITStargazers:1Issues:4Issues:0
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akashlevy.github.io

My personal website (based on HTML5 Up Identity theme)

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dctk

Delay Calculation ToolKit

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Digital-IDE

all in one vscode plugin for Verilog/VHDL development

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ember-digital

Digital components of EMBER memory macro

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ember-fpga

EMBER Vivado project for Genesys2

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ember-pcb

PCB for interfacing the EMBER macro with FPGA, power supplies, probing, and power measurement

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gdsiistl

Converts GDSII files to STL files.

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Genesys2-ClockGen

Clock generator for Genesys2

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NI-RRAM-Python

NI RRAM programming in Python

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NI-RRAM-Test-Setup

LabVIEW code for testing Skywater chips

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NVSim

NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)

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oh

Verilog library for ASIC and FPGA designers

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OpenABC-D

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

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reproduced-papers.github.io

Index web site for reproduced papers

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SetCardGame

A webapp that is the set card game

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Solve24

Solves the game 24 using brute force

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sunburst-chart

A sunburst interactive chart web component for visualizing hierarchical data

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vscode-verilog-hdl-support

HDL support for VS Code

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