memory-design

There are 1 repository under memory-design topic.

aieask / mdw21
Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
analog-design circuit-design ieee memory memory-design sram-cell sram-memories
Language:AGS Script 17
akashlevy / pyxbar
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
python spice hspice netlist waveform generator simulation circuit memory-design rram nvm verilog-a testbench
Language:SourcePawn 13
AhmedIssa11 / Compiler-Design
lexical-analyzer syntax-analyzer semantic-analyzer memory-design compiler-design csharp
Language:C# 4
AkhilRai28 / Single-Port-RAM
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog
Language:Verilog 3
jtsimons / DRAMC
Behavioral architecture of a read/write cycle controller for a DRAM chip.
digital-design dram fpga memory-controller memory-design tcl vhdl
Language:VHDL 1
LijinWilson / 8---bit-RAM
This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.
advanced btech-project memory memory-design mtechprojects nptel-solutions ram test-bench verilog vlsi-design
Language:Verilog 1
Pranavh-2004 / 64KB_RAM_iverilog
PESU Sem 3: Mini project for Digital Design and Computer Organization
digital-design-and-computer-organization hdl memory-design modular-design ram verilog
Language:Verilog 0
VLSI-Shubh / SRAM
SRAM Collection – Parameterized Verilog Modules for Single Port SRAM (sync/async read), Pseudo Dual Port SRAM (sync read), and True Dual Port SRAM – all parameterized, fully synthesizable, and demo’d with testbenches and waveforms.
cache-memory dual-port-memory memory-design sram verilog vlsi-design
Language:Verilog

memory-design

aieask / mdw21

akashlevy / pyxbar

AhmedIssa11 / Compiler-Design

AkhilRai28 / Single-Port-RAM

jtsimons / DRAMC

LijinWilson / 8---bit-RAM

Pranavh-2004 / 64KB_RAM_iverilog

VLSI-Shubh / SRAM