BYU Configurable Computing Lab

spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

bfat

Bitstream Fault Analysis Tool

bfasst

Tools for FPGA Assurance Flows

spydrnet-tmr

TMR utilities for the SpyDrNet project

byuccl.github.io

BYU CCL website

digital_design_colab

Digital Design Colab Examples

f4pga-classroom

bitrec

Python/Tcl tools for documenting Xilinx bitstreams. Lead author Corey Simpson.

dac_sdc_2022

iprec

Xilinx CoreGen module recognition project. Lead author Corey Simpson.

WaFoVe

digital_design_colab_archive

edalize

An abstraction library for interfacing EDA tools

fpga-programmer

physical_netlist

prjxray

Documenting the Xilinx 7-series bit-stream format.

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

f4pga

Documentation for F4PGA

f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

litedram

Small footprint and configurable DRAM core

litex

Build your hardware, easily!

mpsoc-rad-selftest

nb_js_diagrammers

Magics and JS for Rendering Diagrams in Jupyter Notebooks

polarfire-soc-bare-metal-examples

Bare metal example software projects for PolarFire SoC

prjxray-db

Project X-Ray Database: XC7 Series

rowhammer-tester

rr_graph_folding

Repository for folding VTR's Routing Resource Graph

short_circuit_aging

vcd_diff

yinstruments

Python code to interact with lab instruments (power analyzer/oscilliscope)