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MasterPlayer / axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

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fpgasystemveriloguartuart-txuart-rxxilinxartixzynqaxi-stream

axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

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FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

fpgasystemveriloguartuart-txuart-rxxilinxartixzynqaxi-stream

License:MIT License

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Language:SystemVerilog 100.0%