standard-cells
There are 0 repository under standard-cells topic.
emu-russia / psxcpu
Reverse engineering of the SONY PlayStation CPU.
Language:C++ 25- globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
7 track standard cells for GF180MCU provided by GlobalFoundries.
Language:Verilog 22 - globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
9 track standard cells for GF180MCU provided by GlobalFoundries.
Language:Verilog 16 - skywater-pdk-libs-sky130_fd_sc_hd
"High density" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 14 en9inerd / SimAn
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Language:C++ 9- skywater-pdk-libs-sky130_fd_sc_hdll
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 4 - skywater-pdk-libs-sky130_fd_sc_hs
"High speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 4 - skywater-pdk-libs-sky130_fd_sc_ls
"Low speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 4 - skywater-pdk-libs-sky130_fd_sc_ms
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 4 - skywater-pdk-libs-sky90fd_fd_sc
Standard cells for SKY90FD provided by SkyWater.
- skywater-pdk-libs-sky130_fd_sc_hvl
"High voltage" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 3 - skywater-pdk-libs-sky130_fd_sc_lp
"Low power" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 3 - skywater-pdk-libs-sky90fd_osu_sc
Standard cells for SKY90FD provided by Oklahoma State University.
rgznelson / stdcell-characterizer
Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06
Language:Python 0A 12-track height standard cell library built in SKY130 PDK. The cells were designed using Magic VLSI Layout Tool and characterized using Digital Standard Cell Characterizer (DSCC).
Language:Python 0