HEP-SoC

SoCMake

CMake based hardware build system

common_cells

Common SystemVerilog components

svuvm-socmake

SystemVerilog UVM SoCMake package

apb_crc_uvm_socmake

cluster_interconnect

PeakRDL-halcpp

C++ 17 Hardware abstraction layer generator from systemrdl

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

PeakRDL-socgen

picorv32_socmake

PicoRV32 - A Size-Optimized RISC-V CPU

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

tech_cells_generic

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

UVVM_SoCMake

UVVM SoCMake support repository