Risto Pejašinović's repositories
PeakRDL-halcpp
C++ 17 Hardware abstraction layer generator from systemrdl
PeakRDL-opentitan
SystemRDL <-> Opentitan regtool hjson format exporter, importer
vrpark_remap
Remapping app for cheap Aliexpress joystick modules to be used with Kodi or other player
Cores-VeeR-EL2
VeeR EL2 Core
crave
Constrained random stimuli generation for C++ and SystemC
lecroy_dso
Simple library to get some measurements from lecroy oscilloscope over PyVisa
mini-gdbstub
Fork with Cmake files
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
stanford_cg635_gpib
PyVisa GPIB class for stanford CG635 clock generator
systemc-ams
SystemC-AMS fork
systemc-compiler
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
systemrdl-compiler
SystemRDL 2.0 language compiler front-end
verilator
Verilator open-source SystemVerilog simulator and lint system
verilog-i2c
Verilog I2C interface for FPGA implementation
verisc_as_dep
Example project of using VeriSC as a dependency in a CMake project, the VeriSC will build itself and check the version, update if needed
xmake-docs
The xmake online documentation site