Risto97 / systemc_uvm_verilator

systemc uvm accellera verilator pygears verilog fpga

This is archived.

Check this project instead:

https://github.com/Risto97/systemc_uvm_env

Working example for SystemC-UVM and Verilator simulation

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systemc uvm accellera verilator pygears verilog fpga

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Language:C++ 72.5%Language:Makefile 23.6%Language:Python 4.0%