nelsoncsc

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ARM Ltd

United Kingdom

https://sistenix.com

Nelson Campos's repositories

ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

Language:SystemVerilogMIT86 100

easyUVM

A simple UVM example with DPI

Language:SystemVerilogMIT36 4 1

sv_image

Reusable image processing modules in SystemVerilog

Language:SystemVerilogMIT33 40

FFT

Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm

Language:SystemVerilog14 4 1

basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

Language:SystemVerilogMIT9 30

sv_math

Reusable math modules (multiplication, division, square root and logarithm) in SystemVerilog

Language:SystemVerilogMIT7 30

smarts

This repository contains several examples and problems in Modern Control including: neural networks, expert systems, genetic algorithms.The codes are implemented in Matlab/Octave and CLIPS. Each task has its own description in a pdf report. The overview of the all tasks can be seen in the file smarts.pdf

Language:MATLABMIT4 30

basic_uvmc

A simple testbench with two refmods using UVM Connect

Language:SystemVerilogMIT3 20

FIR_FILTER

FIR Filter Generation and Audio Processing in Altera DE2

Language:VerilogNOASSERTION3 20

systems-id

This repository contains several examples and problems in Systems Identification and Estimation.The codes are implemented in Matlab/Octave.

Language:MATLABMIT2 20

ADUC_7026

This repository contains an implementation of the Protocol I2C using the microncontroller ADUC 7026. The communication is between one master with two slaves.

Language:CMIT1 20

basicSV

Very basic SystemVerilog examples

Language:SystemVerilogMIT1 20

cello

Genetic circuit design automation

Language:JavaBSD-2-Clause1 20

gameboy

Exploring Game Boy programming techniques.

Language:HTMLMIT1 20

hls_tutorials

Tutorials on HLS Design

Language:C++Apache-2.01 10

keras

Deep Learning library for Python. Convnets, recurrent neural networks, and more. Runs on TensorFlow or Theano.

Language:PythonNOASSERTION1 20

QuartusBuildVMs

Details for installing Quartus on Linux (via VMs and Docker containers) to create build machines for Altera FPGA projects

1 20

UPF-Demo

Unified Power Format Demo (in System Verilog and UPF)

Language:Stata1 20

litex

Build your hardware, easily!

Language:CNOASSERTION000

nelsoncsc

Config files for my GitHub profile.

010

nelsoncsc.github.io

sistenix.com

Language:HTMLMIT010

red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

Language:CMIT000

verilog-axis

Verilog AXI stream components for FPGA implementation

Language:PythonMIT000