SingularityKChen's repositories
langchain-vlsi-flow
LangChain based VLSI flow that is able to generate required HDL, testbench, design creation and implementaion scripts.
Weekly_Review_in_NTU
The weekly reviews.
chisel-chipware
The Chisel wrapper for Cadence Chipware reusable IP blocks. It does not conatin any implementation details of the IPs.
SingularityKChen.github.io
My Persional Blog
automl
Google Brain AutoML
barstools
Useful utilities for BAR projects
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chisel-template
A template project for beginning new Chisel work
chiseltest
The official testing library for Chisel circuits.
constellation
A Chisel RTL generator for network-on-chip interconnects
detectron2
Detectron2 is a platform for object detection, segmentation and other visual recognition tasks.
dsptools
A Library of Chisel3 Tools for Digital Signal Processing
faster-rcnn.pytorch
A faster pytorch implementation of faster r-cnn and fine tune for ShapoolNMS.
FasterTransformer
Transformer related optimization, including BERT, GPT
firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
gemmini
Berkeley's Spatial Array Generator
hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
riscv-sodor
educational microarchitectures for risc-v isa
rocket-chip
Rocket Chip Generator
rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generator
rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
rocket-dsp-utils
Tools for integrating DspTools components into a rocket-chip
ultralytics
NEW - YOLOv8 🚀 in PyTorch > ONNX > CoreML > TFLite