Performed an ASIC Design flow for UART including design, verification and physical design. ∗ Developed the interface with a customizable baud generator, transmitter, FIFO with a parity-bit checker, and a receiver. ∗ Also, the design is simultaneously taken to GDSII by using OpenLane, an open-source flow from RTL to GDSII with a skywater 130nm technology node. ∗ The UART is verified by a UVM environment having a scoreboard, sequencer, driver, and monitor.