control-unit

There are 0 repository under control-unit topic.

mck-sbs / PyConSys
Python Control System : Create control loops and let the AI set the PID parameters
python ai pid control-loops evolutionary-algorithms control-systems control-unit pygad
Language:Python 30
mck-sbs / Pendulum
Inverted Pendulum in python with pybox2d. Fuzzy and PID simulation included.
pid inverted-pendulum control control-unit pybox2d control-systems control-loop fuzzy
Language:Python 9
arasgungore / NandGame
Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.
arithmetic-logic-unit computer control-unit digital-design logic-gates logic-programming logic-unit memory nandgame processor switching hardware binary-logic fundamentals-of-computing solutions arithmetic-circuits nand-game random-access-memory logic-circuit thenandgame-solutions
6
EmreKumas / Processor_Design
This is an implementation of a simple CPU in Logisim and Verilog.
cpu cpu-design cpu-simulation register-file data-memory address-memory instructions alu control-unit assembler logisim modelsim
Language:Verilog 5
gabrielganzer / VHDL-DesignSynthesis
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
vhdl verilog synthesis digital-design rtl scripts tcl polito booth-multiplier register-file windowed-register-file control-unit adder-subtractor physical-design subtractor
Language:Verilog 4
eneskzlcn / Datapath
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
logisim datapath register-file alu data-memory instructions instruction-memory control-unit program-counter
2
EslamAsHhraf / Pipelined-Processor
🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.
cufe-2024 processor python verilog computer-architecture instrumentation pipline pipline-operators control-unit registers execution-unit memory program-counter state-machine buffers pipelined-processor
Language:Verilog 2
0marAmr / Single_Cycle_RISC-V_processor
alu control-unit datapath processor risc-v verilog verilog-hdl fpga fpga-programming vivado memory digital-design
Language:Verilog 1
claudiomarpda / control_unit
Implementation of a microprogrammed control unit for didactic purpose
cache computer-architecture control-unit cpu memory register
Language:C 1
ryanvickr / Taillight-Control-Unit
An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.
altera control-unit cyclone-v taillight vhdl
Language:VHDL 1
suly520 / VisuProject
Software for 3-axis machine control. It uses a Raspberry Pi with motor controllers and additional electronics. Features: visualization, GPIO emulation, touchscreen capability, and Cython optimization. Tested on Windows(visu) and Raspberry Pi OS. Under development with Pyside2 and OpenGl.
python python3 opengl pyqt5 pyside2 3d circuit diploma-project gui-application motor-driver visualization control-unit raspberry-pi raspberry-pi-4 gpio raspberrypi wavefront-obj py qt-designer
Language:Python 1
beyzanc / 18-bit-processor-implementation-using-logisim
18-bit processor implementation using Logisim
alu circuit-design control-unit finite-state-machine instruction-set-architecture logisim processor-design
Language:Python 0
IshanMK / 8-bit-single-cycle-cpu
simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.
control-unit register single-cycle-processor verilog
Language:Verilog 0
keonhee-han / Control-Unit-Design-VHDL-
vhdl fpga control-unit
0
mehmetakifkoz / CENG3010-Computer-Organization
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
16-bit-cpu code-execution computer-architecture control-unit cpu-design custom-processor gui-dashboard instruction-set-architecture logic-circuits mips-simulator processor-design simulation user-interface
Language:JavaScript 0
NajimAlfutini / Design-A-Full-SRC-Processor
The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.
alu control-unit cpu isa memory pipeline
Language:HTML 0
soaresfabricio / x86-control-unit
A control unit simulator capable of running GAS syntax assembly.
assembly control-unit gas-syntax simulator x86
Language:C++ 0
DoniaGameel / Pipelined-Processor-using-verilog
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
pipelined-processors control-unit alu assembler hazard-detection branch-prediction full-forwarding
Language:Verilog
ksajan / Control_Unit_Simulation
Using Python creating simulation of Control unit
python3 control-unit microprogrammed-control-unit computer-organisation-architechure
Language:Python
meysam81 / ram-datapath-and-Control-Unit
from back in the university, a digital design laboratory project, designing a data path and control unit of ram
college-assignment laboratory ram data-path control-unit proteus
parissashahabi / Logisim-RISC-Processor-Design
16 bit processor designed in logisim
assembler processor verilog alu control-unit register-file cpu risc-processor mips
Language:Verilog

control-unit

mck-sbs / PyConSys

mck-sbs / Pendulum

arasgungore / NandGame

EmreKumas / Processor_Design

gabrielganzer / VHDL-DesignSynthesis

eneskzlcn / Datapath

EslamAsHhraf / Pipelined-Processor

0marAmr / Single_Cycle_RISC-V_processor

claudiomarpda / control_unit

ryanvickr / Taillight-Control-Unit

suly520 / VisuProject

beyzanc / 18-bit-processor-implementation-using-logisim

IshanMK / 8-bit-single-cycle-cpu

keonhee-han / Control-Unit-Design-VHDL-

mehmetakifkoz / CENG3010-Computer-Organization

NajimAlfutini / Design-A-Full-SRC-Processor

soaresfabricio / x86-control-unit

DoniaGameel / Pipelined-Processor-using-verilog

ksajan / Control_Unit_Simulation

meysam81 / ram-datapath-and-Control-Unit

parissashahabi / Logisim-RISC-Processor-Design