windowed-register-file

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gabrielganzer / VHDL-DesignSynthesis
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
adder-subtractor booth-multiplier control-unit digital-design physical-design polito register-file rtl scripts subtractor synthesis tcl verilog vhdl windowed-register-file
Language:Verilog 4

gabrielganzer / VHDL-DesignSynthesis