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Advanced Architecture Labs with CVA6
LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator
These scripts are used in a Vivado project, to implement jtag to axi transactions. The general project is to run baremetal cpp code on Ariane RISC-V core
Provides baremetal support for the CVA6 COREV APU on GENESYS2
Our work as students (Team Breizh Hat) for the national CVA6 softcore hackathon organized by Thales Group